LG eyes entry into HBM race with advanced packaging

LG Electronics is developing a next-generation chip packaging method essential to boosting the power efficiency of high bandwidth memory (HBM) chips, heralding a potential entry into the new, lucrative business.

LG Electronics' Production-engineering Research Institute(PRI) in Pyeongtaek, Gyeonggi [PRI]

LG Electronics is developing a next-generation chip packaging method essential to boosting the power efficiency of high bandwidth memory (HBM) chips, heralding a potential entry into the new, lucrative business.

Dubbed hybrid bonding, the technique could allow for higher chip stacking and capacity by using direct copper-to-copper bonding, and major chipmakers like Samsung Electronics and SK hynix plan to adopt it for their future HBM ranges.

“LG’s Production-engineering Research Institute is researching and developing the technology as a part of its endeavor to develop new chip packaging and testing methods,” a spokesperson at LG Electronics said on Monday.

The confirmation came after Seoul Economic Daily reported that the Korean electronics maker will enter the hybrid bonding business with an aim of mass-producing the new product in 2028, a claim that the spokesperson called premature.

“We are reviewing the business without any buyer decided”, while declining to confirm the reported target year.

Local component suppliers like Hanmi Semiconductor, Hanwha Semitech and Samsung’s subsidiary Semes have all bet on the yet-to-be-commercialized packaging technique.

So far, both SK hynix and Samsung Electronics, the world’s two largest HBM makers, have relied on conventional packaging techniques called TC bonding or mass reflow-mold underfill, but hybrid bonding is considered the key to migrating into future generation chips.

Industry observers expect Samsung Electronics to apply hybrid bonding technology to its sixth-generation HBM4 chips, while SK hynix will likely introduce it with its seventh-generation HBM4E memory.

As the semiconductor industry faces physical and economic limits for further advancing chip performance during manufacturing, chip packaging — or the manufacturing of the casing that surrounds a semiconductor — has become a new battleground.

Some processors and system-on-chips have already integrated hybrid bonding.

BY PARK EUN-JEE [park.eunjee@joongang.co.kr]