KAIST, Samsung Electronics to partner up for BCDMOS chip

[Graphics by Kim Eo-jin]

The Korea Advanced Institute of Science and Technology (KAIST) said that the national research university would sign a partnership deal with Samsung Electronics Co. on Tuesday for the 130nm Bipolar CMOS DMOS (BCDMOS) technology.

Samsung Electronics has collaborated with the IC Design Education Center (IDEC), a research institution run by KAIST, since 2021 to provide students with chip fabrication opportunities for 28nm logic process chips while nurturing semiconductor design talent.

The BCDMOS technology integrates analog circuits, logic circuits, and high-voltage devices on a single chip, making it ideal for power management applications that require high-voltage and high-speed operation. KAIST and Samsung Electronics will adopt the BCDMOS 8-inch process in the second half of 2024 to offer master‘s and doctoral students majoring in semiconductor design and engineering across 13 universities the opportunity to gain experience in chip fabrication.