Samsung to mass produce world’s first 300-layer NAND chips in 2024

Lee Jung-bae, president of memory business at Samsung Electronics. [Courtesy of Samsung Electronics]

South Korea’s tech giant Samsung Electronics Co. announced Tuesday that it will mass produce 300-layer NAND flash memory chips for the first time in the world in early 2024, advancing the production timeline by one year compared to SK hynix Inc. which was the first to develop 321-layer NAND memory.

Samsung Electronics plans to take the lead in the 300-layer NAND production with an aim to strengthen its market dominance.

“We are developing the double-stack structured 9th-generation V-NAND (Vertical-NAND), which is the highest layer that can be realized,” said Lee Jung-bae, president of memory business at Samsung Electronics.

His remarks were made in a contribution posted on the company’s website. “We have successfully secured the operational chips for mass production early next year.”

The securing of operational chips indicates that the final preparations for mass production are in the final stages.

The announcement of the plan comes ahead of Samsung Memory Tech Day 2023 that is scheduled to kick off Friday.

Samsung Electronics plans to develop 1,000-layer V-NAND by 2030.

NAND, unlike DRAM, is a type of memory that can store data even when the power is turned off. The higher the stacking of NAND layers, the more storage capacity can be achieved within the same area, making it a measure of technological prowess.

Industry insiders expect the competition for NAND to intensify.

In August, SK hynix unveiled its 321-layer NAND for the first time at the Flash Memory Summit 2023 in the U.S.

The chip reportedly utilizes a triple-stack approach where three separate chips are created and then vertically assembled.

Samsung Electronics, on the other hand, has adopted a double-stack structure, which involves only two stacks, even for layers exceeding 300. This means Samsung’s process involves fewer steps, potentially saving time and cost.

Samsung Electronics has been focusing on stacking the highest number of layers with the smallest number of stacks.

While SK hynix and Micron Technology Inc. applied double-stack technology from 72 layers, Samsung Electronics utilized single-stack technology up to 128 layers.

In the contribution, Lee also revealed the company’s goal of maximizing density by reducing cell interference and size, which implies that even with the construction of “ultra-high-rise NAND apartments,” the overall height will be kept as similar as possible.

“We will continue to enhance our strengths in minimizing inter-cell interference and achieving the industry’s smallest cell size,” Lee said. “We are also developing innovative technologies, including a new structure to maximize input and output speed.”

Samsung Electronics has minimized cell size through its three-dimensional (3D) scaling technology, reducing not only the planar and vertical aspects but also the volume by up to 35 percent, making it easier to control interference even when creating chips with the same number of layers as competitors but with lower cell height.

Lee also expressed confidence that Samsung Electronics would demonstrate overwhelming technological capabilities in high bandwidth memory (HBM).

“We are already mass-producing HBM3 and are actively developing the next-generation product, HBM3E,” said Lee. “We will supply the best solutions by utilizing our technology proven through many years of mass production experience and partnerships with customers.”