Samsung sets stage for HBM4 with DRAM tech breakthrough

(Kim Ho-young)

Samsung Electronics Co. took a bold step in the race for next-generation memory dominance as it completed the development of its sixth-generation DRAM. This latest innovation is expected to serve as securing the foundation for responding to high-bandwidth memory (HBM) 4.

It improved the ‘central wiring layer’ structure, which acts as a key passage for power and signal exchanges within the chip, as well as improving heat generation and performance issues. Improving the central wiring layer structure has been challenging until now, and with its recent success, Samsung Electronics could have entered a turning point to regain the leadership in memory technology.

The company’s memory business division announced on Tuesday that it achieved product readiness approval (PRA) for DRAM manufactured with its 1c process of 10-nanometer, signaling readiness to move forward with yield stabilization and rigorous customer validation. PRA is granted when technical criteria for mass production are met, but the product still needs to pass yield stabilization, quality standards, and reliability tests.

D1c is Samsung Electronics’ latest DRAM process. It is the sixth generation based on a 10nm-class roadmap following 1x, 1y, 1z, 1a, and 1b. With each new generation, Samsung Electronics continues to push circuit miniaturization further by improving memory performance, reducing power consumption, and increasing density.

This process is characterized by an ultra-fine design that applies extreme ultraviolet (EUV) exposure equipment to multiple layers. It reduces cell interference and leakage current by completely replacing the insulation structure and materials, while simultaneously securing heat control capability and yield stability.

The company paid particular attention to improving the central wiring layer structure, which had been a design bottleneck during this development process but is a key path that distributes power and control signals to memory cells within the DRAM. The wiring density increases as the process becomes more sophisticated, which worsens heat generation and signal interference problems, but the company successfully increased power transmission efficiency and thermal stability while reducing the wiring area.

Samsung Electronics is known to have actively recruited external semiconductor design experts since the second half of 2024 and redesigned the central wiring layer, which improved the production yield to over 60%. This technology is considered suitable for application in the production of future next-generation HBM products, as it has achieved a yield that meets customer supply standards.

The company plans to turn the tables in the HBM4 competition with this achievement while also planning to provide HBM4 samples based on the 1c process to customers in the second half of 2025 and promote quality tests (quality verification). As SK Hynix grows its market share with its HBM3E 12-layer offering, Samsung Electronics is likely to speed up HBM4 commercialization to remain competitive.

SK Hynix currently leads the HBM market after successfully mass producing the world’s first HBM3E 12-layer based on the 1b process while also supplying HBM4 samples to major customers. SK Hynix will provide memory for NVIDIA’s next-generation GPU, making it a crucial partner for the world’s leading HBM provider.

For its part, Samsung Electronics has also been conducting customer tests with products based on the existing 1a to 1b processes as it aims for a turnaround in terms of yield and reliability through the introduction of this 1c process and structural improvement. The company plans to expand the application of the 1c process to premium memory products such as high-performance server DRAM and DDR5 as well as HBM4.

The early commercialization of HBM4 will impact the AI semiconductor market, with yield management and customer certification strategies now crucial for the future success of the global semiconductor industry.