Samsung Chief Jay Y. Lee visits ZEISS to bolster foundry business

(Second from left) Jay Y. Lee, Executive chairman of Samsung Electronics, poses for a photo during his visit to ZEISS headquarters on April 26, 2024. [Photo provided by Samsung Electronics Co.]

Jay Y. Lee, executive chairman of Samsung Electronics Co., visited the headquarters of global optics company ZEISS Group in Germany to discuss potential partnerships.

Lee visited the ZEISS headquarters in Oberkochen, Germany, on Friday, and discussed cooperation in the field of nanometer processes, the company said on Sunday.

ZEISS is the exclusive supplier of optical systems to ASML Holding N.V., the Dutch manufacturer of extreme ultraviolet (EUV) lithography systems.

“Collaboration with ZEISS will enable us to improve the performance and production processes of next-generation semiconductors and increase yield,” Samsung Electronics said.

The company added that it aims to lead the sub-3-nanometer ultra-fine process in the foundry market and start mass production of 6th-generation, 10-nanometer DRAMs using EUV processes by the end of the year.

Lee‘s visit to Germany follows the recent announcement by competitor Taiwan Semiconductor Manufacturing Co. (TSMC) of its 1.6-nanometer process roadmap.

TSMC, which previously planned a 2-nanometer process by 2025 and a 1.4-nanometer process by 2027, has set off a race with its 1.6-nanometer process roadmap.

Samsung Electronics, however, is confident that its Gate-All-Around (GAA) technology will make it the market leader in the 2-nanometer process.

Originally developed by Samsung Electronics, GAA technology offers superior power efficiency and performance compared to conventional fin-shaped field-effect transistor (FinFET) structures.

The chipmaker successfully mass-produced 3-nanometer chips using GAA technology in 2022 for the first time in the world.

[Photo provided by Samsung Electronics Co.]

Samsung Electronics is the only company to use GAA technology in its foundry process, while TSMC has plans to begin the use from the 2-nanometer process, although it faces lower yields than TSMC.

Lee has discussed yield improvement measures with ZEISS executives.

“Expanding cooperation on EUV technology and advanced equipment will improve yield,” the company said, adding that the pilot application of digital twin technology using artificial intelligence and big data in chip manufacturing will begin next year.

With the increasing complexity of fine processes, the importance of packaging has been growing.

Samsung Electronics has been accelerating the development and commercialization of X-Cube, a 3D packaging technology, and building the 20 trillion won ($14.5 billion) next-generation semiconductor research and development (R&D) complex at its Giheung facilities.

Lee has also been active in holding talks with global technology CEOs about AI chip cooperation.

In February, he met with Meta Platforms Inc.’s Mark Zuckerberg in Seoul, and early last year he held meetings with ASML‘s Peter Wennink and Nvidia Corp.’s Jensen Huang.

In 2019, Lee declared the “System Semiconductor Vision 2030,” under which the company aims to lead the system chip market by increasing investment to 171 trillion won from 133 trillion won.