SK hynix, TSMC to collaborate on HBM4 chips

The partnership will extend to the development of next-generation high bandwidth memory chips, with an emphasis on packaging for efficiency.

SK hynix headquarters in Icheon, Gyeonggi [NEWS1]

Korean memory giant SK hynix will extend its partnership with Taiwan's TSMC to collaborate on the development of next-generation high bandwidth memory (HBM) chips, known as HBM4.

Their HBM4 is slated to begin mass production from 2026.

The two will primarily focus on improving the packaging system of new HBM chips — more specifically, the performance of the base die at the very bottom, which connects to the graphic processing unit (GPU) that controls the HBM.

Before, SK hynix used proprietary technology to make base dice up to HBM3E, but will now adopt TSMC’s advanced logic process for the HBM4’s base die, which will enable the company to produce customized HBM for clients seeking a specific performance and power efficiency.

The partners will also work to integrate the Taiwanese firm's proprietary packaging process known as “chip on wafer on substrate” in the Korean chipmaker's HBM, and also jointly respond to client requests pertaining to the manufacturing process.

Chip on wafer on substrate, or CoWoS, is a multi-chip packaging technology that integrates multiple dice horizontally on a silicon interposer in order to achieve better density and performance.

“We expect a strong partnership with TSMC to help accelerate our efforts for open collaboration with our customers and develop the industry’s best-performing HBM4,” said Justin Kim, President and the Head of AI Infra, at SK hynix. “With this cooperation in place, we will strengthen our market leadership as the total AI memory provider further by beefing up competitiveness in the space of the custom memory platform.”

Rival chipmaker Samsung Electronics plans to complete the development of 16-layered HBM4 chips by next year, according to Youn Jae-youn, vice president of DRAM development at the company's device solution division, on its website. The chipmaker plans to employ advanced thermal nonconductive film (TC NCF) technology that will effectively excrete heat in HBM packaging, the company explained.

Samsung said that it completed the development of 12-layered HBM3E chips in February.

BY LEE JAE-LIM [lee.jaelim@joongang.co.kr]